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M48Z128 M48Z128Y
1 Mbit (128Kb x8) ZEROPOWER(R) SRAM
s
INTEGRATED LOW POWER SRAM, POWER-FAIL CONTROL CIRCUIT and BATTERY CONVENTIONAL SRAM OPERATION; UNLIMITED WRITE CYCLES 10 YEARS of DATA RETENTION in the ABSENCE of POWER AUTOMATIC POWER-FAIL CHIP DESELECT and WRITE PROTECTION WRITE PROTECT VOLTAGES (VPFD = Power-fail Deselect Voltage): - M48Z128: 4.50V VPFD 4.75V - M48Z128Y: 4.20V VPFD 4.50V
s
32 1
s
s
PMDIP32 (PM) Module SNAPHAT (SH) Battery
s
s
BATTERY INTERNALLY ISOLATED UNTIL POWER IS APPLIED PIN and FUNCTION COMPATIBLE with JEDEC STANDARD 128K x 8 SRAMs SURFACE MOUNT CHIP SET PACKAGING INCLUDES a 28-PIN SOIC and a 32-LEAD TSOP (SNAPHAT TOP TO BE ORDERED SEPARATELY) SOIC PACKAGE PROVIDES DIRECT CONNECTION for a SNAPHAT TOP WHICH CONTAINS the BATTERY SNAPHAT(R) HOUSING (BATTERY) IS REPLACEABLE
17 A0-A16 M48Z128 M48Z128Y
TSOP32 (8 x 20mm) SOH28
s
s
Surface Mount Chip Set Solution (CS)
s
Figure 1. Logic Diagram
s
VCC
Table 1. Signal Names
A0-A16 DQ0-DQ7 E G W VCC VSS NC June 2000 Address Inputs Data Inputs / Outputs Chip Enable Output Enable
8 DQ0-DQ7
W E G
Write Enable Supply Voltage Ground Not Connected Internally 1/17
VSS
AI01194
M48Z128, M48Z128Y
Table 2. Absolute Maximum Ratings (1)
Symbol TA TSTG TBIAS TSLD (2) V IO VCC Parameter Ambient Operating Temperature Storage Temperature (V CC Off) Temperature Under Bias Lead Solder Temperature for 10 seconds Input or Output Voltages Supply Voltage Value 0 to 70 -40 to 70 -10 to 70 260 -0.3 to 7 -0.3 to 7 Unit C C C C V V
Note: 1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to the absolute maximum rating conditions for extended periods of time may affect reliability. 2. Soldering temperature not to exceed 260C for 10 seconds (total thermal budget not to exceed 150C for longer than 30 seconds).
CAUTION: Negative undershoots below -0.3V are not allowed on any pin while in the Battery Back-up mode.
Table 3. Operating Modes
Mode Deselect Write Read Read Deselect Deselect VSO to VPFD (min) VSO 4.75V to 5.5V or 4.5V to 5.5V VCC E VIH VIL VIL VIL X X G X X VIL VIH X X W X VIL VIH VIH X X DQ0-DQ7 High Z D IN DOUT High Z High Z High Z Power Standby Active Active Active CMOS Standby Battery Back-up Mode
Note: 1. X = VIH or VIL; VSO = Battery Back-up Switchover Voltage.
Figure 2. DIP Connections
NC A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS 1 32 2 31 3 30 4 29 5 28 6 27 7 26 8 M48Z128 25 9 M48Z128Y 24 10 23 11 22 12 21 13 20 14 19 15 18 16 17
AI01195
VCC A15 NC W A13 A8 A9 A11 G A10 E DQ7 DQ6 DQ5 DQ4 DQ3
DESCRIPTION The M48Z128/128Y ZEROPOWER(R) RAM is a 128 Kbit x8 non-volatile static RAM that integrates power-fail deselect circuitry and battery control logic on a single die. The monolithic chip is available in two special packages to provide a highly integrated battery backed-up memory solution. The M48Z128/128Y is a non-volatile pin and function equivalent to any JEDEC standard 128K x8 SRAM. It also easily fits into many ROM, EPROM, and EEPROM sockets, providing the non-volatility of PROMs without any requirement for special write timing or limitations on the number of writes that can be performed. The 32 pin 600mil DIP Module houses the M48Z128/128Y silicon with a long life lithium button cell in a single package. For surface mount environments ST provides a Chip Set solution consisting of a 28 pin 330mil SOIC NVRAM Supervisor (M40Z300) and a 32 pin TSOP (8 x 20mm) LPSRAM (M68Z128) packages. The 28 pin 330mil SOIC provides sockets with gold plated contacts at both ends for direct connection to a separate SNAPHAT housing containing the battery.
2/17
M48Z128, M48Z128Y
Figure 3. Block Diagram
VCC
A0-A16
POWER E VOLTAGE SENSE AND SWITCHING CIRCUITRY
131,072 x 8 SRAM ARRAY
DQ0-DQ7
E W G
INTERNAL BATTERY
VSS
AI01196
The unique design allows the SNAPHAT battery package to be mounted on top of the SOIC package after the completion of the surface mount process. Insertion of the SNAPHAT housing after reflow prevents potential battery damage due to the high temperatures required for device surfacemounting. The SNAPHAT housing is keyed to prevent reverse insertion. The SNAPHAT battery package is shipped separately in plastic anti-static tubes or in Tape & Reel form. The part number is "M4Z28-BRxxSH1". The M48Z128/128Y also has its own Power-fail Detect circuit. The control circuitry constantly monitors the single 5V supply for an out of tolerance condition. When VCC is out of tolerance, the circuit write protects the SRAM, providing a high degree of data security in the midst of unpredictable system operation brought on by low VCC. As VCC falls below approximately 3V, the control circuitry connects the battery which maintains data until valid power returns.
READ MODE The M48Z128/128Y is in the Read Mode whenever W (Write Enable) is high and E (Chip Enable) is low. The device architecture allows ripple-through access of data from eight of 1,048,576 locations in the static storage array. Thus, the unique address specified by the 17 Address Inputs defines which one of the 131,072 bytes of data is to be accessed. Valid data will be available at the Data I/O pins within Address Access time (t AVQV) after the last address input signal is stable, providing that the E and G (Output Enable) access times are also satisfied. If the E and G access times are not met, valid data will be available after the later of Chip Enable Access time (tELQV) or Output Enable Access Time (tGLQV). The state of the eight threestate Data I/O signals is controlled by E and G. If the outputs are activated before t AVQV, the data lines will be driven to an indeterminate state until tAVQV. If the Address Inputs are changed while E and G remain low, output data will remain valid for Output Data Hold time (t AXQX) but will go indeterminate until the next Address Access.
3/17
M48Z128, M48Z128Y
Figure 4. Hardware Hookup for SMT Chip Set (1)
THS(2) SNAPHAT BATTERY(3)
VOUT
VCC E2
M40Z300 E E1CON E2CON E3CON E4CON A RST B BL VSS W E
M68Z128 DQ0-DQ7
A0-A16
VSS
AI03625
Note: 1. For pin connections, see individual data sheets for M40Z300 and M68Z128 at www.st.com. 2. Connect THS pin to VOUT if 4.2V VPFD 4.5V (M48Z128Y) or connect THS pin to VSS if 4.5V VPFD 4.75V (M48Z128). 3. SNAPHAT ordered separately.
Table 4. AC Measurement Conditions
Input Rise and Fall Times Input Pulse Voltages Input and Output Timing Ref. Voltages 5ns 0 to 3V 1.5V
Figure 5. AC Testing Load Circuit
5V
Note that Output Hi-Z is defined as the point where data is no longer driven.
1.9k DEVICE UNDER TEST 1k
OUT
CL = 100pF or 5pF
CL includes JIG capacitance
AI01030
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M48Z128, M48Z128Y
Table 5. Capacitance (1, 2) (TA = 25 C, f = 1MHz)
Symbol C IN CIO (3) Parameter Input Capacitance Input / Output Capacitance Test Condit ion VIN = 0V VOUT = 0V Min Max 10 10 Unit pF pF
Note: 1. Effective capacitance measured with power supply at 5V. 2. Sampled only, not 100% tested. 3. Outputs deselected.
Table 6. DC Characteristics (TA = 0 to 70 C; VCC = 4.75V to 5.5V or 4.5V to 5.5V)
Symbol ILI (1) ILO (1) ICC ICC1 ICC2 VIL VIH VOL VOH Parameter Input Leakage Current Output Leakage Current Supply Current Supply Current (Standby) TTL Supply Current (Standby) CMOS Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage IOL = 2.1mA IOH = -1mA 2.4 Test Conditio n 0V VIN VCC 0V VOUT VCC E = VIL, Outputs open E = VIH E VCC - 0.2V -0.3 2.2 Min Max 1 1 105 7 4 0.8 VCC + 0.3 0.4 Unit A A mA mA mA V V V V
Note: 1. Outputs deselected.
Table 7. Power Down/Up Trip Points DC Characteristics (1) (TA = 0 to 70 C)
Symbol VPFD V SO tDR (2) Parameter M48Z128 Power-fail Deselect Voltage M48Z128Y Battery Back-up Switchover Voltage Data Retention Time 10 4.2 4.3 3 4.5 V V YEARS Min 4.5 Typ 4.6 Max 4.75 Unit V
Note: 1. All voltages referenced to VSS. 2. At 25 C.
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M48Z128, M48Z128Y
Table 8. Power Down/Up AC Characteristics (TA = 0 to 70 C)
Symbol tF (1) tFB (2) tWP tR tER Parameter V PFD (max) to VPFD (min) VCC Fall Time V PFD (min) to VSO VCC Fall Time Write Protect Time from VCC = VPFD V SO to VPFD (max) VCC Rise Time E Recovery Time Min 300 10 40 0 40 120 150 Max Unit s s s s ms
Note: 1. VPFD (max) to VPFD (min) fall time of less than tF may result in deselection/write protection not occurring until 200s after VCC passes VPFD (min). 2. VPFD (min) to VSO fall time of less than tFB may cause corruption of RAM data.
Figure 6. Power Down/Up Mode AC Waveforms
VCC VPFD (max) VPFD (min) VSO tF tFB tWP E
RECOGNIZED
tDR
tR
tER DON'T CARE
RECOGNIZED
HIGH-Z OUTPUTS VALID
(PER CONTROL INPUT)
VALID
(PER CONTROL INPUT)
AI01031
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M48Z128, M48Z128Y
Table 9. Read Mode AC Characteristics (TA = 0 to 70 C; VCC = 4.75V to 5.5V or 4.5V to 5.5V)
M48Z128/M48Z128Y Symbol Parameter Min tAVAV tAVQV (1) tELQV (1) tGLQV (1) tELQX (2) tGLQX (2) tEHQZ (2) tGHQZ (2) tAXQX (1) Read Cycle Time Address Valid to Output Valid Chip Enable Low to Output Valid Output Enable Low to Output Valid Chip Enable Low to Output Transition Output Enable Low to Output Transition Chip Enable High to Output Hi-Z Output Enable High to Output Hi-Z Address Transition to Output Transition 5 5 3 30 20 5 70 70 70 35 5 3 35 25 10 -70 Max Min 85 85 85 45 5 3 45 35 -85 Max Min 120 120 120 60 -120 Max ns ns ns ns ns ns ns ns ns Unit
Note: 1. CL = 100pF. 2. CL = 5pF.
Figure 7. Address Controlled, Read Mode AC Waveforms
tAVAV A0-A16 tAVQV VALID tAXQX
DQ0-DQ7
DATA VALID
AI01078
Note:
Chip Enable (E) and Output Enable (G) = Low, Write Enable (W) = High.
7/17
M48Z128, M48Z128Y
Figure 8. Chip Enable or Output Enable Controlled, Read Mode AC Waveforms
tAVAV A0-A16 tAVQV tELQV E tELQX tGLQV G tGLQX DQ0-DQ7 DATA OUT
AI01197
VALID tAXQX tEHQZ
tGHQZ
Note: Write Enable (W) = High.
WRITE MODE The M48Z128/128Y is in the Write Mode whenever W and E are active. The start of a write is referenced from the latter occurring falling edge of W or E. A write is terminated by the earlier rising edge of W or E. The addresses must be held valid throughout the cycle. E or W must return high for minimum of tEHAX from E or tWHAX from W prior to the initiation of another read or write cycle. Data-in must be valid tDVWH prior to the end of write and remain valid for tWHDX or tEHDX afterward. G should be kept high during write cycles to avoid bus contention; although, if the output bus has been activated by a low on E and G, a low on W will disable the outputs tWLQZ after W falls. DATA RETENTION MODE With valid VCC applied, the M48Z128/128Y operates as a conventional BYTEWIDETM static RAM. Should the supply voltage decay, the RAM will automatically power-fail deselect, write protecting it-
self tWP after VCC falls below VPFD. All outputs become high impedance, and all inputs are treated as "don't care." If power fail detection occurs during a valid access, the memory cycle continues to completion. If the memory cycle fails to terminate within the time tWP, write protection takes place. When VCC drops below VSO, the control circuit switches power to the internal energy source which preserves data. The internal coin cell will maintain data in the M48Z128/128Y after the initial application of VCC for an accumulated period of at least 10 years when VCC is less than VSO. As system power returns and VCC rises above VSO , the battery is disconnected, and the power supply is switched to external VCC. Write protection continues for tER after VCC reaches VPFD to allow for processor stabilization. After tER, normal RAM operation can resume. For more information on Battery Storage Life refer to the Application Note AN1012.
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M48Z128, M48Z128Y
Table 10. Write Mode AC Characteristics (TA = 0 to 70 C; VCC = 4.75V to 5.5V or 4.5V to 5.5V)
M48Z128/M48Z128Y Symbol Parameter Min tAVAV tAVWL tAVEL tWLWH tELEH tWHAX tEHAX tDVWH tDVEH tWHDX tEHDX tWLQZ (1, 2) tAVWH tAVEH tWHQX (1, 2) Write Cycle Time Address Valid to Write Enable Low Address Valid to Chip Enable Low Write Enable Pulse Width Chip Enable Low to Chip Enable High Write Enable High to Address Transition Chip Enable High to Address Transition Input Valid to Write Enable High Input Valid to Chip Enable High Write Enable High to Input Transition Chip Enable High to Input Transition Write Enable Low to Output Hi-Z Address Valid to Write Enable High Address Valid to Chip Enable High Write Enable High to Output Transition 65 65 5 70 0 0 55 55 5 15 30 30 0 10 25 75 75 5 -70 Max Min 85 0 0 65 75 5 15 35 35 0 10 30 100 100 5 -85 Max Min 120 0 0 85 100 5 15 45 45 0 10 40 -120 Max ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit
Note: 1. CL = 5pF. 2. If E goes low simultaneously with W going low after W going low, the outputs remain in the high impedance state.
POWER SUPPLY DECOUPLING and UNDERSHOOT PROTECTION ICC transients, including those produced by output switching, can produce voltage fluctuations, resulting in spikes on the VCC bus. These transients can be reduced if capacitors are used to store energy, which stabilizes the VCC bus. The energy stored in the bypass capacitors will be released as low going spikes are generated or energy will be absorbed when overshoots occur. A ceramic bypass capacitor value of 0.1F (as shown in Figure 9) is recommended in order to provide the needed filtering. In addition to transients that are caused by normal SRAM operation, power cycling can generate negative voltage spikes on V CC that drive it to values below VSS by as much as one Volt. These negative spikes can cause data corruption in the SRAM while in battery backup mode. To protect from these voltage spikes, it is recommended to connect a schottky diode from VCC to VSS (cathode connected to VCC, anode to VSS). Schottky diode 1N5817 is recommended for through hole and MBRS120T3 is recommended for surface mount.
Figure 9. Supply Voltage Protection
VCC VCC
0.1F
DEVICE
VSS
AI02169
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M48Z128, M48Z128Y
Figure 10. Write Enable Controlled, Write AC Waveforms
tAVAV A0-A16 VALID tAVWH tAVEL E tWLWH tAVWL W tWLQZ tWHDX DQ0-DQ7 DATA INPUT tDVWH
AI01198
tWHAX
tWHQX
Note: Output Enable (G) = High.
Figure 11. Chip Enable Controlled, Write AC Waveforms
tAVAV A0-A16 VALID tAVEH tAVEL E tAVWL W tEHDX DQ0-DQ7 DATA INPUT tDVEH
AI01199
tELEH
tEHAX
Note: Output Enable (G) = High.
10/17
M48Z128, M48Z128Y
Table 11. Ordering Information Scheme
Example: Device Type M48Z Supply Voltage and Write Protect Voltage 128 = VCC = 4.75V to 5.5V; VPFD = 4.5V to 4.75V 128Y = VCC = 4.5V to 5.5V; VPFD = 4.2V to 4.5V Speed -70 = 70ns -85 = 85ns -120 = 120ns Package PM = PMDIP32 CS (1) = Surface Mount Chip Set solution M40Z300 (SOH28) + M68Z128 (TSOP32) Temperature Range 1 = 0 to 70 C
Note: 1. The SOIC package (SOH28) requires the battery package (SNAPHAT ) which is ordered separately under the part number "M4Zxx-BR00SH1" in plastic tube or "M4Zxx-BR00SH1TR" in Tape & Reel form. Caution: Do not place the SNAPHAT battery package "M4Zxx-BR00SH1" in conductive foam since this will drain the lithium button-cell battery.
M48Z128Y
-70 CS
1
For a list of available options (Speed, Package, etc...) or for further information on any aspect of this device, please contact the STMicroelectronics Sales Office nearest to you. Table 12. Revision History
Date May 1999 04/13/00 06/20/00 First Issue Document Layout changed Surface Mount Chip Set solution added tGLQX changed (Table 9) Revision Details
11/17
M48Z128, M48Z128Y
Table 13. PMDIP32 - 32 pin Plastic Module DIP, Package Mechanical Data
mm Symbol Typ A A1 B C D E e1 e3 eA L S N Min 9.27 0.38 0.43 0.20 42.42 18.03 2.29 34.29 14.99 3.05 1.91 32 0.59 0.33 43.18 18.80 2.79 41.91 16.00 3.81 2.79 Max 9.52 Typ Min 0.365 0.015 0.017 0.008 1.670 0.710 0.090 1.350 0.590 0.120 0.075 32 0.023 0.013 1.700 0.740 0.110 1.650 0.630 0.150 0.110 Max 0.375 inches
Figure 12. PMDIP32 - 32 pin Plastic Module DIP, Package Outline
A
A1 S B e3 D e1
L eA
C
N
E
1 PMDIP
Drawing is not to scale.
12/17
M48Z128, M48Z128Y
Table 14. SOH28 - 28 lead Plastic Small Outline, battery SNAPHAT, Package Mechanical Data
mm Symbol Typ A A1 A2 B C D E e eB H L N CP 1.27 0.05 2.34 0.36 0.15 17.71 8.23 - 3.20 11.51 0.41 0 28 0.10 Min Max 3.05 0.36 2.69 0.51 0.32 18.49 8.89 - 3.61 12.70 1.27 8 0.050 0.002 0.092 0.014 0.006 0.697 0.324 - 0.126 0.453 0.016 0 28 0.004 Typ Min Max 0.120 0.014 0.106 0.020 0.012 0.728 0.350 - 0.142 0.500 0.050 8 inches
Figure 13. SOH28 - 28 lead Plastic Small Outline, battery SNAPHAT, Package Outline
A2 B e
A C eB CP
D
N
E
H A1 L
1 SOH-A
Drawing is not to scale.
13/17
M48Z128, M48Z128Y
Table 15. M4Z28-BR00SH SNAPHAT Housing for 48 mAh Battery, Package Mechanical Data
mm Symbol Typ A A1 A2 A3 B D E eA eB L 0.46 21.21 14.22 15.55 3.20 2.03 6.73 6.48 Min Max 9.78 7.24 6.99 0.38 0.56 21.84 14.99 15.95 3.61 2.29 0.018 0.835 0.560 0.612 0.126 0.080 0.265 0.255 Typ Min Max 0.385 0.285 0.275 0.015 0.022 0.860 0.590 0.628 0.142 0.090 inches
Figure 14. M4Z28-BR00SH SNAPHAT Housing for 48 mAh Battery, Package Outline
A1
A2 A A3
eA D
B eB
L
E
SHZP-A
Drawing is not to scale.
14/17
M48Z128, M48Z128Y
Table 16. M4Z32-BR00SH SNAPHAT Housing for 120 mAh Battery, Package Mechanical Data
mm Symbol Typ A A1 A2 A3 B D E eA eB L 0.46 21.21 17.27 15.55 3.20 2.03 8.00 7.24 Min Max 10.54 8.51 8.00 0.38 0.56 21.84 18.03 15.95 3.61 2.29 0.018 0.835 0.680 0.612 0.126 0.080 0.315 0.285 Typ Min Max 0.415 0.335 0.315 0.015 0.022 0.860 0.710 0.628 0.142 0.090 inches
Figure 15. M4Z32-BR00SH SNAPHAT Housing for 120 mAh Battery, Package Outline
A1
A2 A A3
eA D
B eB
L
E
SHZP-A
Drawing is not to scale.
15/17
M48Z128, M48Z128Y
Table 17. TSOP32 - 32 lead Plastic Thin Small Outline, 8 x 20 mm, Package Mechanical Data
mm Symbol Typ A A1 A2 B C D D1 e E L CP N 32 0.500 0.050 0.950 0.150 0.100 19.800 18.300 - 7.900 0.500 0 Min Max 1.200 0.150 1.050 0.270 0.210 20.200 18.500 - 8.100 0.700 5 0.100 32 0.0197 0.0020 0.0374 0.0059 0.0039 0.7795 0.7205 - 0.3110 0.0197 0 Typ Min Max 0.0472 0.0059 0.0413 0.0106 0.0083 0.7953 0.7283 - 0.3189 0.0276 5 0.0039 inch
Figure 16. TSOP32 - 32 lead Plastic Thin Small Outline, 8 x 20 mm, Package Outline A2
1 N
e E B
N/2
D1 D
A CP
DIE
C
TSOP-a
A1
L
Drawing is not to scale.
16/17
M48Z128, M48Z128Y
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in lif e support devices or systems without express written approval of STMicroelectronics. The ST logo is registered trademark of STMicroelectronics (R) 2000 STMicroelectronics - All Rights Reserved All other names are the property of their respective owners. STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A . http://w ww.st.com
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